ITHome October 23 news: In an interview on the Dwarkesh podcast, Intel Chief Technology Officer (CTO) Pushkar Ranade said:Even with ample funding, global cutting-edge wafer output would struggle to expand tenfold, with a more realistic growth ceiling of about two times.
On the podcast, Ranade was asked "whether the world has enough tools to raise leading-edge wafer output 10 times". He responded: "Not 10 times, but possibly 2 times, yes." He believes this limitation stems from the ability of the entire semiconductor supply chain to expand capacity in coordination, rather than from any single link.
According to the blog post cited by ITHome, Ranade pointed out that AI compute capacity has grown at roughly three times per year over the past decade, but the critical equipment, cleanrooms, and fab scale needed to manufacture advanced chips are becoming the new capacity ceiling.
Among these, ASML produces fewer than 100 EUV lithography machines per year, and it will be difficult to significantly expand output even by the end of this decade, while Intel, TSMC, and memory makers such as SK Hynix all compete for these machines.
He further explained that equipment ordered today usually takes about 18 months to be delivered, meaning capacity will not materialize until around 2028. Newly built fabs also cannot automatically bring more wafers, an important reason being that equipment supply cannot keep up.
Ranade explained that to raise overall output, equipment suppliers, their upstream suppliers, and even lower-tier sub-suppliers must all increase capacity in sync. In other words, if any single link — lithography machines, critical components, materials, inspection equipment, or factory construction — becomes a "bottleneck", the final output of advanced wafers will struggle to leap significantly.