IT Home On November 11, Huawei Kirin’s official account published an article detailing the first “logical folding” technology τ chip — the new generation Da Vinci architecture NPU of the Kirin 9050 series. This chip supports the running of large-scale models on-device with 30B parameters and features the ability to operate without internet or cloud services.
New generation Da Vinci architecture NPU performance improved by 140%, power consumption reduced by 66%Supports the Transformer engine, the ultra-low power consumption perception engine, and the CANN heterogeneous computing architecture;The first 30B MoE large model client end in the industrySupports multi-level storage and computation collaboration optimization, low-bit quantization.
In terms of specific features, the new generation Da Vinci architecture NPU offers capabilities such as Perceptual Screen - AI Screen Reading, Perceptual Image - Xmage Smart Capture 2.0, Perceptual Human Eye - AI Eye Movement Page Turning, and Perceptual Location - Power-Off Map 2.0.
According to previous reports by IT Home, at the 2026 Kirin Media Communication Meeting held by Huawei in October this year, Xu Songyu, Director of Wireless Terminal Chip Product Management for Huawei’s semiconductor business, said that the Kirin 9050 series, as the first logic-folding τ chip, will usher in a new journey for the next 10 years. The PPT shows that Huawei aims to break through 5GHz for the P-core frequency by 2031.