On October 12, 2026, MemSilicon announced the completion of tape-out for its first-generation high-density, large-capacity RRAM chip "MountTai 2026," based on the 1TnR technology route.
"MountTai 2026" is a milestone for MemSilicon in advancing 1TnR high-density, large-capacity emerging memory chip technology from early-stage research to Gb-level chip productization. This technology route improves storage capacity per unit area by having multiple resistive memory cells share a selection transistor, and uses a back-end-of-line integration approach fully compatible with the CMOS platform, achieving density, capacity and cost simultaneously.
The chip uses a 28nm CMOS process platform and a 1T4R cell structure, with a single-chip capacity of 1Gb, density of 30Mb/mm², access latency of less than 20ns, and integrated on-chip hardware error correction circuitry. It achieves a coordinated breakthrough in large capacity, high density and high-speed reading, providing an internationally competitive solution for on-chip high-density, large-capacity emerging non-volatile memory applications.
Currently, "MountTai 2026" has completed tape-out and verification is underway.
Package image of "MountTai 2026"
01 Surging demand calls for the optimal solution in density, capacity and process compatibility
From high-performance SoCs to embodied intelligence, AI PCs and other smart terminals, chips need to accommodate more weights, KV Cache, parameters and data while controlling access latency, power consumption and cost. Memory must not only "fit it all," but also meet continuously growing capacity demands under on-chip integration conditions suitable for mass production.
Different memory technologies each have strengths and constraints. SRAM offers fast access but large memory cell area and low density; embedded Flash carries the important task of program and data storage, but integration difficulty increases as logic processes shrink. RRAM, which combines non-volatility with the potential for high-density integration, has therefore become the mainstream emerging memory technology solution.
Public reports show that major global foundries including Samsung, TSMC and GlobalFoundries have already included RRAM in their technology roadmaps for advanced process nodes. Among them, TSMC's technology roadmap explicitly includes RRAM in its support for the 12nm and 6nm nodes. On the customer side, Infineon has selected an RRAM solution for its 28nm microcontrollers.
In targeting the RRAM market, especially the high-density, large-capacity demand segments, MemSilicon actively explores the 1TnR route because, beyond reducing product cost, its more important role is enabling more memory cells to be integrated on limited chip area, meeting the needs of storing and computing larger-scale model parameters.
02 From 1T1R to 1T4R: from pioneering the technology route to the first large-capacity chip tape-out
RRAM stores information through changes in the resistance state of materials, and data is retained even after power loss. In the common 1T1R structure, one selection transistor corresponds to one resistive memory cell: the transistor is responsible for selecting and controlling access, while the resistive cell stores information.
As resistive cells shrink in size, the area occupied by the selection transistor and its interconnect structure becomes a problem that must be solved to further increase density. The idea of 1TnR is to have one selection transistor correspond to multiple resistive memory cells, reducing the transistor area overhead allocated to each memory cell.
As the international pioneer of the CMOS-standard-process-compatible 1TnR technology route, MemSilicon's technical expertise originates from the team of Academician Liu Ming of the Chinese Academy of Sciences. As early as 2020, the research team had publicly disclosed 28nm 1T2R RRAM research.
"MountTai 2026" adopts a 1T4R structure, where one selection transistor corresponds to four resistive memory cells. But sharing the transistor does not mean density and performance increase proportionally with the number of memory cells. Non-target current paths between multiple memory cells, read/write disturbances, and reliability under different operating conditions all require joint optimization of devices, processes and circuit design.
Addressing the core technical challenges of large-capacity RRAM chips with 1TnR structure, the "MountTai 2026" chip introduced and validated for the first time a series of independent innovations at the circuit and architecture levels: introducing a negative voltage design and unified reset circuit method to significantly suppress array leakage current, reducing chip power consumption and improving reliability; designing multi-voltage-domain wordline driver circuits to achieve complete decoupling of high- and low-voltage read/write paths, and proposing an adaptive protection bias voltage technique to effectively reduce erroneous-write risk and comprehensively improve write reliability; developing an on-chip adaptive follow reading circuit to overcome the read reliability and read yield challenges 1TnR faces at Gb-level large capacity, and, together with hardware error correction circuitry, building a dual read guarantee mechanism of "circuit adaptivity + hardware error correction".
Based on a 28nm back-end-compatible process, "MountTai 2026" combines comprehensive advantages of high performance, high density, high reliability and low power consumption, marking the company's systematic breakthrough in key circuit technologies for large-capacity on-chip RRAM chips, with good industrialization prospects and broad application space.
03 Echoing policy, advancing three lines in parallel
In September this year, the "14th Five-Year-to-15th Five-Year" development plan for the electronics information manufacturing industry, jointly issued by the Ministry of Industry and Information Technology and the National Development and Reform Commission, has listed emerging memory products such as resistive memory and computing paradigms such as compute-in-memory among development directions.
MemSilicon, whose core team originates from the Chinese Academy of Sciences and Fudan University, actively responds to policy, continuously strengthening its independently developed product portfolio around embedded memory, large-capacity memory and hybrid compute-in-memory needs.
The first product line is embedded RRAM IP, targeting applications such as display drivers, microcontrollers, SSD controllers and security chips, providing embedded RRAM IP that has already entered customer scenarios and is expanding application scale.
The second product line is high-density, large-capacity RRAM, further exploring different structures such as 1TnR and further 3D integration around increasing integration density, expanding single-chip capacity and improving standalone product form, as well as memory needs related to AI inference.
The third product line is hybrid compute-in-memory combining RRAM and DRAM, targeting embodied intelligence, AI PCs and other edge inference scenarios. Through hybrid 3D integration, it explores ways for different memory technologies and computing units to collaborate, shortening data movement paths and achieving the best balance among capacity, bandwidth and energy consumption.
Overall, driven by both favorable policy and technological breakthroughs, MemSilicon is poised, as an independently innovative emerging memory force, to make important contributions to consolidating China's memory-and-computing foundation.